179.

F. Senicar, M. Döpker, A. Bartsch, B. Krüger and S. Soter, "Inverter based method for measurement of PMSM machine parameters based on the elimination of power stage characteristics" in IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, 2014, pp. 702--708.

Abstract:
This paper presents the precise measurement of the stator inductance as well as the stator resistance, using an inverter. Precise measurement results are created, although the actual output voltage of the inverter is not known exactly. This paper analyzes the different effects of an output power stage, and how they degrade the quality of the output voltage. This knowledge is used to cancel out this output voltage error in enabling a precise measurement of the machine parameters. This allows an easy auto commissioning of the current controller and furthermore an auto commissioning of an optimal torque control. The presented methods are verified with extensive measurement results.

178.

T. Boller, J. Holtz and A. K. Rathore, "Neutral point potential balancing using synchronous optimal pulsewidth modulation of multilevel inverters in medium voltage high power AC drives" in 2014 IEEE Energy Conversion Congress and Exposition (ECCE), 2014, pp. 4802--4807.

Abstract:
This paper presents neutral point potential (NPP) balancing while maintaining low harmonic distortion using optimal pulsewidth modulation (PWM) of multilevel inverter for medium voltage high power industrial AC drives. This method is applicable for five-level inverters or higher. High performance of the machine is observed experimentally at low switching frequency operation employing the proposed technique. In the past, low distortion and optimal common mode voltage at low switching frequency control have been reported using proposed synchronous optimal pulse modulation.

177.

A. Edpuganti, A. K. Rathore and J. Holtz, "New optimal pulsewidth modulation for single DC-link dual inverter fed open-end stator winding induction motor drives" in 2014 IEEE Energy Conversion Congress and Exposition (ECCE), 2014, pp. 3865--3871.

Abstract:
The multilevel topologies of dual inverters feeding an open-end stator winding induction motor has been introduced around two decades ago. However, these topologies require common-mode inductor in series with motor windings to suppress zero-sequence or common-mode currents. In medium-voltage high power drives, low device switching frequencies are preferred to improve the overall efficiency of drive system. On the other hand, low device switching frequencies leads to higher total harmonic distortion (THD) of stator currents. Therefore, the objective of our study was to propose a new optimal pulsewidth modulation to eliminate zero-sequence currents and minimize harmonic distortion of stator currents, while operating power semiconductor devices at low device switching frequencies. The main idea is to select switching patterns such that all zero-sequence components are eliminated and then, perform optimization for every steady-state operating point to minimize the THD of stator currents. The proposed modulation has been validated on dual two-level and dual three-level inverters fed 1.5-kW open-end stator winding Induction motor drive.

176.

T. Boller, J. Holtz and A. K. Rathore, "Optimal pulsewidth modulation of a dual three-level inverter system operated from a single dc link" in 2014 IEEE Energy Conversion Congress and Exposition (ECCE), 2014, pp. 3406--3410.

Abstract:
Operating a dual three-level inverter system from a single dc link circuit is an economic solution for generating five-level output voltage waveforms and to double the output power compared to a single three-level inverter. Such inverter system is used for feeding a drive motor with open stator windings. A mechanism is then required to reduce the common mode voltage components of the motor voltages. This paper describes an off-line optimization method that minimizes both the harmonic distortion of the motor currents and the common mode voltage components. The optimization permits reducing the switching frequency to a very low value of 200 Hz without compromising on harmonic distortion. High performance operation of the drive system at low switching frequency is experimentally demonstrated.

175.

A. K. Rathore, J. Holtz and T. Boller, "Optimal pulsewidth modulation of multilevel inverters for low switching frequency control of medium voltage high power industrial AC drives" in 2014 IEEE Energy Conversion Congress and Exposition (ECCE), 2014, pp. 4569--4574.

Abstract:
This paper presents an optimal pulsewidth modulation (PWM) technique for low switching frequency control of multilevel inverters for medium voltage high power industrial AC drives applications. Synchronous optimal PWM permits setting the maximum switching frequency to a low value without compromising in THD. Low switching frequency reduces the switching losses of the power semiconductor devices, resulting in higher inverter power output and efficiency. Experimental results of a five-level inverter drive using optimal PWM are presented. Two types of topologies are discussed: 1) Isolated dc link topology and 2) Common dc link topology with common mode inductor.

174.

A. Bartsch, K. Klitzke, F. Senicar and S. Soter, "Optimized design of a scalable FPGA based inverter by implementing an application-specific instruction-set processor" in IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, 2014, pp. 1672--1678.

Abstract:
This paper presents an improvement of a field programmable gate array (FPGA) based scalable inverter drive to control electrical machines. In order to enhance the average utilization of the resources (logic cells and dedicated hardware) of the FPGA, an application-specific instruction-set processor (ASIP) is designed and implemented on the FPGA. To promote better organization of the source code, it is possible to write instructions in a MATLAB based syntax, which are translated into the instruction set for the ASIP.

173.

A. Uphues, K. Nötzold, R. Wegener, K. Fink, M. Bragard, R. Griessel and S. Soter, "Inverter based test setup for LVRT verification of a full-scale 2 MW wind power converter" in 2013 15th European Conference on Power Electronics and Applications (EPE), 2013, pp. 1--5.

Abstract:
With increased wind power penetration, grid codes of system operators require low voltage ride through (LVRT) capability for wind turbines (WT). This paper describes a full power test bench, designed to evaluate the functionality of grid connected converter in nominal operating mode and in case of LVRT. To verify the LVRT capability an inverter based voltage sag generator (VSG) is developed which emulates grid failures.

172.

A. Uphues, K. Nötzold, R. Wegener, S. Soter and R. Griessel, "Support of grid voltages with asymmetrical reactive currents in case of grid errors" in 2013 IEEE International Conference on Industrial Technology (ICIT), 2013, pp. 1781--1786.

Abstract:
Due to the increasing wind power penetration, grid codes of system operators require low voltage ride through (LVRT) capability for wind turbines (WT). Additionally the WT has to support the power system stability in LVRT cases by supporting the grid with reactive power. By feeding symmetrical reactive currents in case of asymmetrical grid errors, as required in many actual grid codes, the phase voltage of the undistorted phase will increase above the upper voltage limit. This paper shows a strategy to feed asymmetrical reactive currents into the distorted grid without increasing the phase voltage in the undistorted phase.

171.

A. Uphues, K. Nötzold, R. Wegener and S. Soter, "SOGI based grid fault detection for feeding asymmetrical reactive currents to fulfill LVRT requirements" in 2013 IEEE AFRICON, 2013, pp. 1--5.

Abstract:
Due to the increasing wind power penetration, grid codes of system operators require low voltage ride through (LVRT) capability for wind turbines (WT). Additionally the WT has to support the power system stability in LVRT cases by supporting the grid with reactive power. The amount of reactive power feed-in depends on the type of grid fault and the depth of the voltage dip. Therefore this paper shows a reliable grid voltage monitoring consisting on a second order generalized integrator (SOGI) structure. The resulting phase locked loop (PLL) is tolerant against grid faults and the amplitudes and phase angles of the individual phase voltages are detected.

170.

A. Bartsch, F. Senicar, S. Kratz and S. Soter, "Enhanced FPGA based three level space vector pulse width modulation with active neutral point balancing" in 2013 IEEE Energy Conversion Congress and Exposition, 2013, pp. 1748--1753.

Abstract:
This paper presents an FPGA based implementation of an improved space vector pulse width modulation for neutral point clamped three-level topologies. For this purpose the flatspace modulation calculating the timings is used in combination with an optimized switching pattern to reduce the switching edges to a minimum. Additionally a combination of two methods for balancing the neutral point is developed which are both implemented without adding any additional harmonics to the modulated output.